Waiting for POST to change
Post 37 - SHA_COMPUTE_4BL_CD
Post 06
Post 86 - Panic - EXTERNAL
Post 8E - Panic - VPU_UNAVAILABLE
Post C7 - LZX_EXPAND_7
Post 01
Post F8
Post 7F
Post 09
Post 07
Post C3 - LZX_EXPAND_3
Post E0
Post E0
Post 04
Post 01
Post 1A - RC4_INITIALIZE
Post 30 - VERIFY_OFFSET_4BL_CD
Post 07
Post 1E - BRANCH
Post 7C
Post E0
Post 85 - Panic - INSTRUCTION_SEGMENT
Post E0
Post C0
Post 01
Post 3C
Post 48 - SHA_COMPUTE
Post E0
Post 03
Post 08
Post E0
Post 1F
Post C0
Post 7C
Post 60 - INIT_KERNEL
Post F8
Post E0
Post 3C
Post 8D - Panic - TRACE
Post E0
Post 07
Post E0
Post 71 - INIT_AUDIO_DRIVER
Post 01
Post 48 - SHA_COMPUTE
Post E0
Post F8
Post E0
Post C0
Post 03
Post E0
Post E0
Post 8C - Panic - SYSTEM_CALL
Post 04
Post 48 - SHA_COMPUTE
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 07
Post 3F
Post 0C
Post 18 - FETCH_CONTENTS
Post 41 - VERIFY_OFFSET
Post C2 - LZX_EXPAND_2
Post E0
Post C7 - LZX_EXPAND_7
Post 0D
Post 86 - Panic - EXTERNAL
Post 04
Post E0
Post 44 - FETCH_CONTENTS
Post 80
Post E0
Post 30 - VERIFY_OFFSET_4BL_CD
Post 10 - Payload/1BL started
Post C1 - LZX_EXPAND_1
Post 40 - Entrypoint of CD reached
Post E0
Post E0
Post C0
Post 18 - FETCH_CONTENTS
Post FE
Post 61 - INIT_HAL_PHASE_0
Post E0
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 88 - Panic - PROGRAM
Post 86 - Panic - EXTERNAL
Post 20 - CB entry point reached
Post 1A - RC4_INITIALIZE
Post 12 - FSB_CONFIG_RX_STATE
Post 08
Post 03
Post C3 - LZX_EXPAND_3
Post 8F - Panic - MAINTENANCE
Post 8F - Panic - MAINTENANCE
Post 18 - FETCH_CONTENTS
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post FC
Post E0
Post C3 - LZX_EXPAND_3
Post 07
Post 18 - FETCH_CONTENTS
Post 1F
Post E0
Post E0
Post C3 - LZX_EXPAND_3
Post 03
Post A0 - Panic - VERIFY_SECOTP_6
Post 82 - Panic - DATA_STORAGE
Post E0
Post 40 - Entrypoint of CD reached
Post A0 - Panic - VERIFY_SECOTP_6
Post 01
Post 91 - Panic - THERMAL_MANAGEMENT
Post 7F
Post 80
Post 06
Post E0
Post E0
Post 03
Post 1F
Post E0
Post 40 - Entrypoint of CD reached
Post 1F
Post 78 - INIT_STFS_DRIVER
Post E3
Post E0
Post 03
Post E0
Post 60 - INIT_KERNEL
Post E3
Post 18 - FETCH_CONTENTS
Post 10 - Payload/1BL started
Post 9F - Panic - VERIFY_SECOTP_5
Post 01
Post 20 - CB entry point reached
Post 07
Post 80
Post C2 - LZX_EXPAND_2
Post C0
Post 01
Post 03
Post 80
Post 61 - INIT_HAL_PHASE_0
Post 24 - VERIFY_OFFSET_3BL_CC
Post 80
Post 1F
Post E0
Post 41 - VERIFY_OFFSET
Post E0
Post 03
Post 01
Post 60 - INIT_KERNEL
Post 08
Post 40 - Entrypoint of CD reached
Post 03
Post C0
Post FC
Post C0
Post 61 - INIT_HAL_PHASE_0
Post 07
Post C7 - LZX_EXPAND_7
Post E0
Post 12 - FSB_CONFIG_RX_STATE
Post 30 - VERIFY_OFFSET_4BL_CD
Post E0
Post 61 - INIT_HAL_PHASE_0
Post 44 - FETCH_CONTENTS
Post C2 - LZX_EXPAND_2
Post 03
Post 44 - FETCH_CONTENTS
Post 09
Post 01
Post F1 - Panic - VERIFY_HEADER_CB_B
Post 86 - Panic - EXTERNAL
Post 20 - CB entry point reached
Post 18 - FETCH_CONTENTS
Post E0
Post 06
Post 0E
Post 20 - CB entry point reached
Post E0
Post 03
Post E3
Post E0
Post 0C
Post E0
Post 7F
Post 1F
Post E0
Post F8
Post F7
Post E2
Post C2 - LZX_EXPAND_2
Post 82 - Panic - DATA_STORAGE
Post 80
Segnalibri